1. Field
Example embodiments relate to a method of fabricating a memory device and the memory device.
2. Description of the Related Art
As a semiconductor memory device must have a higher integration density, (e.g., a larger number of memory cells per area), a faster operating speed, and operate with less power consumption, research has been conducted and various kinds of memory devices have been developed. A semiconductor memory device may include many memory cells connected in circuits. In a dynamic random access memory (DRAM), which is a typical semiconductor memory device, a unit memory cell normally consists of one switch and one capacitor. The DRAM may have a higher integration density and a faster operating speed. The DRAM, however, may lose all stored data when the power is shutdown.
On the contrary, a typical example of a nonvolatile memory device, in which stored data may be retained even when the power is shut down, is a flash memory device. The flash memory device has a nonvolatile property unlike a volatile memory device, but may have a lower integration density and a slower operating speed compared to the DRAM. Some examples of nonvolatile memory devices that are currently being developed are a magnetic random access memory (MRAM), a ferro-electric random access memory (FRAM) and/or a phase-change random access memory (PRAM). The MRAM stores data using the change of direction of a magnet in a tunnel junction and the FRAM stores data using a polarity property of ferroelectrics. The MRAM and FRAM may have a higher integration density, a faster operating speed, and an ability to operate with less power. The MRAM and FRAM are also being studied and developed to have improved data retention characteristics.
The PRAM stores data using a change in resistance value in accordance with the phase change of a specific material and includes one resistor and one switch (transistor). The resistor used for the PRAM may be a chalcogenide resistor and may have a crystal structure or an amorphous structure by controlling a formation temperature. Because resistance in the amorphous structure is greater than that in the crystal structure, a memory device may be fabricated using these characteristics. When a conventional DRAM process is used in the fabrication of the PRAM, an etching operation may be more difficult and may take a longer time to etch. Productivity may be decreased and the price may increase.
A resistance random access memory (RRAM) may use a transition metal oxide layer as a data storage layer and the resistance value may change in accordance with an applied voltage (e.g., resistance variation characteristics). FIGS. 1A and 1B are diagrams illustrating a typical structure of a RRAM and an artificially current path created in an oxide layer by an applied voltage.
Referring to FIGS. 1A and 1B, an oxide layer 12 and an upper electrode 13 may be formed on a lower electrode 11. The lower electrode 11 and the upper electrode 13 may be composed of a metal (e.g., Ir, Ru, Au, Pt and/or an oxide thereof). The oxide layer 12 may be composed of a transition metal oxide having resistance variation (variable resistance) characteristics. The oxide layer 12 may function as a data storage layer, and by applying a voltage to the oxide layer 12 through the lower electrode 11 and the upper electrode 13, data may be written or recorded data may be read.
When a voltage is applied through the lower electrode 11 and the upper electrode 13, a current may be flowed in the oxide layer 12 by a potential difference. The current may not be distributed evenly in all portions, but may be distributed to form a transient current path 10 inside the oxide layer 12 through crystal grains. As the transient current path 10 formed inside the oxide layer 12 is formed at random, even though the same voltage is applied to the lower electrode 11 and the upper electrode 13, a formation position of the current path 10 and the formation number thereof may change.
FIG. 2 is a graph illustrating a current value in accordance with an applied voltage when a voltage is applied to a memory device including an oxide layer composed of a typical resistance variation material. Particularly, FIG. 2 is a graph illustrating a current flowing through an oxide layer 12 when a given voltage is applied to a lower electrode 11 and an upper electrode 13 of a RRAM having the same structure as that in FIG. 1A. The oxide layer 12 may be composed of nickel oxide (NiO) and the lower electrode 11 and the upper electrode 13 may be composed of Pt.
Referring to FIG. 2, as the voltage applied through the lower electrode 11 and the upper electrode 13 is gradually increased from about 0 V, and when the current value flowing through the oxide layer 12 is measured, the current values may not be the same in every measurement and show slight differences between them. A reset current (RC) may illustrate a difference of ten times even at the same applied voltage, and a set voltage (SV) may not be maintained the same either. As above, as the reset current is unstable and shows a higher value, a reliability of a memory device may be deteriorated and a consumed power may be increased.